As a resistance element incorporated in a semiconductor device, presently a resistance element of polysilicon film is predominantly used. This is because of merits of the good compatibility of the step of forming the resistance element of polysilicon film with the rest process for fabricating the semiconductor device, and the low bias dependency of the resistance element of polysilicon.
Generally, a polysilicon film forming the resistance element is formed concurrently with that forming the gate electrode of a transistor. Accordingly, the resistance element of polysilicon film is formed on the device isolation insulation film defining a device region on the semiconductor substrate or on the gate insulation film. In view of the capacitance with respect to the substrate and the insulation with respect to the substrate, the resistance element is formed mostly on the device isolation insulation film rather than on the gate insulation film.
FIG. 15 is a sectional view of a semiconductor device including a CMOS transistor and a resistance element of polysilicon film, which illustrates a structure thereof.
As illustrated, a device isolation insulation film 102 defining a device region is formed on a silicon substrate 100.
A P well 104 is formed in the silicon substrate 100 in a region for an N type MOS transistor formed in. An N well 106 is formed in the silicon substrate 100 in a region for a P type MOS transistor formed in.
A gate electrode 110n of polysilicon film is formed on the silicon substrate 100 in the region for the N type MOS transistor formed in with a gate insulation film 108 formed therebetween. A sidewall spacer 112 is formed on the side wall of the gate electrode 110n. Source/drain diffused layers 114n of the extension source/drain structure are formed in the silicon substrate 110 on both sides of the gate electrode 110n. Thus, the N type MOS transistor including the gate electrode 110n and the source/drain diffused layers 114n is formed in the region for the N type MOS transistor formed in.
A gate electrode 110p of polysilicon film is formed on the silicon substrate 100 in a region for a P type MOS transistor formed in with the gate insulation film 108 formed therebetween. A sidewall spacer 112 is formed on the side wall of the gate electrode 110p. Source/drain diffused layers 114p of the extension source/drain structure are formed in the silicon substrate 100 on both sides of the gate electrode 110p. Thus, the P type MOS transistor including the gate electrode 110p and the source/drain diffused layers 114p is formed in the region for the P type MOS transistor formed in.
On the device isolation insulation film 102 in a region for a resistance element formed in, a resistance element 116 of polysilicon film with an impurity implanted in is formed. An insulation film 118 is formed on the resistance element 116. The insulation film is not formed in contact parts on both sides of the resistance element 116.
An inter-layer insulation film 120 is formed on the silicon substrate 100 with the N type MOS transistor, the P type MOS transistor and the resistance element 116 formed on. In the inter-layer insulation film 120, there are buried contact plugs 122, 124 electrically connected respectively to the source/drain diffused layers 114n, 114p, contact plugs (not illustrated) electrically connected respectively to the gate electrodes 110n, 110p, and contact plugs 126, 128 connected respectively to the contact parts on both sides of the resistance element 116.
On the inter-layer insulation film 120 with the contact plugs 122–126 buried in, there are formed interconnection layers 130, 132 electrically connected respectively to the source/drain diffused layer 114n, 114p via the contact plugs 122, 124, interconnection layers (not illustrated) electrically connected respectively to the gate electrodes 110n, 110p via the contact plugs, interconnection layers 134, 136 electrically connected respectively to the contact parts on both sides of the resistance element 116 via the contact plugs 126, 128.
Thus, the semiconductor device including the CMOS transistor and the resistance element of polysilicon film is constituted.
In the resistance element incorporated in the semiconductor device as described above, current flows, and electric power is consumed to thereby generate Joule heat. In the semiconductor device having the resistance element formed on the device isolation insulation film as illustrated in FIG. 15, the Joule heat generated in the resistance element escapes mainly into the semiconductor substrate via the device isolation insulation film formed below the resistance element. Accordingly, as the area of the resistance element is larger, the Joule heat generated in the resistance element can escape more easily, and demerits of the resistivity decrease due to the heat generation and the breakage of the resistance element due to the resultant current increase due to the resistivity decrease can be surely prevented.
On the other hand, as the area of the resistance element is smaller, the parasitic capacitance generated between the resistance element and the semiconductor substrate becomes smaller.
As described above, the area of the resistance element must be large so as to ensure the heat radiation of the resistance element while the area of the resistance element must be small so as to decrease the parasitic capacitance. Thus, it is very difficult to make the heat radiation of the resistance element and the parasitic capacitance decrease compatible with each other.
As techniques of ensuring the heat radiation of the resistance element of polysilicon film while decreasing the parasitic capacitance, the techniques disclosed in, e.g., Japanese published unexamined patent application No. Hei 2-283058 (Patent Reference 1), Japanese published unexamined patent application No. Hei 3-248458 (Patent reference 2), Japanese published unexamined patent application No. 2000-150780 (Patent Reference 3) and Japanese published unexamined patent application No. 2001-257317 (Patent Reference 4) are known.
Patent References 1 and 2 disclose the constitution for contacting the resistance element of polysilicon film to the semiconductor substrate outside the contact parts to thereby release the heat generated in the resistance element directly into the substrate. In this constitution, because of the resistance element contacting the substrate, high heat radiation effect can be produced.
Patent Reference 3 discloses the constitution that a polysilicon film of high specific resistance is formed between the resistance element of polysilicon film and the substrate with an insulation film formed therebetween. This constitution, in which the resistance element is in contact with the polysilicon film of high specific resistance and high heat conductivity with the thin insulation film therebetween, allows the heat generated in the resistance element to efficiently escape into the substrate. Since the polysilicon film below the resistance element is thick enough to space the resistance element and the substrate from each other by the thickness of the polysilicon film, the parasitic capacitance is small.
Patent Reference 4 discloses the constitution that the resistance element is extended not only on the thin insulation film but also on the thick insulation film. In this constitution, the heat radiation path to the substrate is ensured via the thick insulation film and also via the protection film formed on the resistance element, which makes it unnecessary to increase the area of the thin insulation film, and no large parasitic capacitance is caused.
However, the constitutions of the semiconductor devices including the resistance elements of polysilcon film disclosed in Patent References 1 to 4 have the following disadvantages which will be described below.
For example, in the constitutions disclosed in Patent References 1 and 2, the potential of the part where the resistance element and the substrate contact with each other must be controlled. In applying this constitution to, e.g., the CMOS circuit, after the gate oxide film has been formed, a contact window for contacting the resistance element and the substrate to each other is opened in the oxide film. It will be necessary to consider the influence of the process of etching, etc. for opening the gate oxide film on the reliability of the gate oxide film.
In applying the constitution disclosed in Patent Reference 3 especially to the CMOS circuit, it is necessary to lay two polysilicon films and pattern for the respective polysilicon films, which will make the steps complicated and increase the fabrication cost.
In the constitution disclosed in Patent Reference 4, in which the resistance element is extended also on the thick insulation film, it is unnecessary to increase the area of the thin insulation film on which the resistance element is formed, but the parasitic capacitance generated in the region for the thin insulation film formed in will not be negligible.
An object of the present invention is to provide a semiconductor device including a resistance element having small parasitic capacitance and good heat radiation.